Conventional asynchronous memory devices rely upon matched memory access signal delays for proper operation. Changing operating conditions and other factors can cause variations in signal timing that can create memory write errors. The following background is provided to more clearly describe this problem.
Static Random Access Memories (SRAMs) are widely used high speed memory devices. The operation of SRAMs is well known and therefore is only briefly described herein. FIG. 1 illustrates a block diagram of an SRAM 110. The controller 122 initiates a memory operation by asserting a chip enable signal 101 and supplying address signals A0-AN (corresponding to 2.sup.N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write operation, the controller 122 supplies the data to be written to the addressed memory location via the bidirectional input/output lines I/O0-I/OK (corresponding to K+1 bit memory words). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bidirectional input/output lines I/O0-I/OK. The memory 110 also provides connections for external power supply (VCC) and ground (GND) signals.
The heart of the memory 110 is the memory array 112, which consists of static memory cells, each capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a write) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via the bit lines BL. When the memory operation is a read, the bit lines BL are coupled to sense amplifiers in the column I/O 120 that sense the data stored in the corresponding cells of the row whose word line WL is active. When the memory operation is a write the bit lines BL carry the signals used to program the corresponding cells of the row associated with the active word line.
The control circuitry 116 controls the other blocks of the memory 110 in response to the chip enable signal 101. Depending on the operation to be performed, the control circuitry issues the appropriate control signals 117a, 117b to the decoder 114 and the I/O data circuit 118, respectively.
Regardless of whether the memory operation is a write or a read, the decoder 114 decodes the address signals A0-AN and activates the word line WL of the row that includes the memory word that is the target of the current memory operation.
If the operation is a write, the I/O data circuitry 118 buffers the input data signals I/O0-I/OK and outputs the buffered data to the column I/O 120 via the bi-directional data bus 119. The column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL0-BLK. The signals on the bit lines BL0-BLK are used to program the cells composing the word whose word line was activated for the current operation by the decoder 114.
If the operation is a read, sense amplifiers (SA) in the column I/O 120 sense the signals on the respective bit lines BL, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via the bi-directional bus 119. The output data are buffered by the I/O data circuit 118 and latched onto the bi-directional data lines I/O0-I/OK for use by the controller 122.
FIG. 2 illustrates a conventional static memory device address control circuit. Y address signals 252 are coupled to decoder 218 and to address transition detection circuit (ATD) 232. The output of decoder 218 is a column select line 258 which couples the corresponding bit line and bit bar line pair to the local I/O bus 264. Similarly the X addresses are coupled to an address transition detection circuit 212 and a decoder 210. The output of decoder 210 drives a word line 260 which selects a memory cell 224.
The X address signal 250 and Y address signal 252 are typically each comprised of a plurality of address lines. Similarly, typically decoder 210 has a plurality of word line outputs, and decoder 218 has a plurality of column select outputs. These word lines and column select lines access an array of memory cells 224. For simplicity, only one small part of this array is illustrated in FIG. 2 with a single memory cell 224.
The address transition detection circuits 212 and 232 output a pulse upon a rising edge or falling edge input transition. Therefore when an X address line or a Y address line changes the corresponding address transition detection circuit outputs a pulse to equalization circuit 242. Equalization circuit 242 equalizes local I/O bus 264 to prevent data from being written while equalization signal 256 is asserted.
A timing diagram for the FIG. 2 conventional static memory device address control circuit is illustrated in FIG. 2A. In FIG. 2A a new Y address is received prior to time t1. These address line transitions cause the EQ 256 signal to switch high at time t1. After EQ 256 switches high column select line 258 and word line 260 are selected. At time t2 the EQ 256 signal is deasserted, and shortly thereafter the write pulse (WPL) 262 signal is asserted. With WPL 262 high, data defined by data lines D 266 and D 268 are written to the selected memory cell.
At the end of a write operation, the X address, Y address, and WEB signals can all change at the same time. The EQ 256 pulse at time t3 is intended to prevent the write pulse from writing data into the memory address for the next cycle. FIG. 2A illustrates the desired timing relationship where the column select and word lines do not change until either the write pulse is at a low level or the equalization signal has been asserted to prevent a high write pulse from writing data. A problem with this type of built-in "hold time" asynchronous memory device is that at the end of a write operation when the X address, Y address and WEB signals change, if an address signal passes through a decoder too quickly then it can cause a column select line or a word line to switch while the write pulse is still high and before the equalization signal has been asserted. This causes the write pulse to write data to the wrong address. In other words, if column select changes before time t3 it causes an error.
Conventional memory devices use delays in the decoder path to attempt to match the decoder path delay and the WEB/WPL 262 path delay so as to avoid writing data to the wrong address. However, because the Y address and the WEB signals typically originate from different locations in the memory chip, they do not track very well. The two signals may track poorly for a variety of reasons including voltages differences at different locations on the chip, different pin locations, variations in the loading conditions and other factors. Variations in the timing relationship between the WEB signal and the Y address signal can cause data to be written to the wrong Y address.
Thus, there is a need for a memory address control circuit that overcomes the Y address and WEB timing problem as well as other problems of the prior art.